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    双极性晶体管

    二极管

    ESD保护、TVS、滤波和信号调节ESD保护

    MOSFET

    氮化镓场效应晶体管(GaN FET)

    绝缘栅双极晶体管(IGBTs)

    模拟和逻辑IC

    汽车应用认证产品(AEC-Q100/Q101)

    74LVC1G332-Q100

    Single 3-input OR gate

    The 74LVC1G332-Q100 is a single 3-input OR gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

    Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

    This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

    This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

    特性

    • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

      • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    • Wide supply voltage range from 1.65 V to 5.5 V

    • High noise immunity

    • Overvoltage tolerant inputs to 5.5 V

    • ±24 mA output drive (VCC = 3.0 V)

    • CMOS low power dissipation

    • Direct interface with TTL levels

    • IOFF circuitry provides partial Power-down mode operation

    • Latch-up performance exceeds 250 mA

    • Complies with JEDEC standard:

      • JESD8-7 (1.65 V to 1.95 V)

      • JESD8-5 (2.3 V to 2.7 V)

      • JESD8C (2.7 V to 3.6 V)

      • JESD36 (4.5 V to 5.5 V)

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    参数类型

    Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
    74LVC1G332GV-Q100Production1.65 - 5.5CMOS/LVTTL± 322.61501low-40~12526163.0172TSOP6
    74LVC1G332GW-Q100Production1.65 - 5.5CMOS/LVTTL± 322.61501low-40~12528456.2172TSSOP6

    封装

    型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
    74LVC1G332GV-Q100
    TSOP6
    (SOT457)     		SOT457REFLOW_BG-BD-1
    WAVE_BG-BD-1
    		SOT457_125ActiveYG74LVC1G332GV-Q100H
    ( 9353 043 65125 )
    74LVC1G332GW-Q100
    TSSOP6
    (SOT363-2)     		SOT363-2SOT363-2_125ActiveYG74LVC1G332GW-Q100H
    ( 9353 043 46125 )

    环境信息

    型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
    74LVC1G332GV-Q10074LVC1G332GV-Q100H74LVC1G332GV-Q100Always Pb-free
    74LVC1G332GW-Q10074LVC1G332GW-Q100H74LVC1G332GW-Q100Always Pb-free
    品质及可靠性免责声明

    文档 (11)

    文件名称标题类型日期
    74LVC1G332_Q100Single 3-input OR gateData sheet2023-08-18
    AN10161PicoGate Logic footprintsApplication note2002-10-29
    AN11009Pin FMEA for LVC familyApplication note2019-01-09
    lvc1g33274LVC1G332 IBIS modelIBIS model2015-09-06
    Nexperia_document_leaflet_Logic_X2SON_packages_062018X2SON ultra-small 4, 5, 6 & 8-pin leadless packagesLeaflet2018-06-05
    Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
    SOT363-2plastic thin shrink small outline package; 6 leads; body width 1.25 mmPackage information2022-11-21
    MAR_SOT457MAR_SOT457 TopmarkTop marking2013-06-03
    WAVE_BG-BD-1Wave soldering profileWave soldering2021-09-08
    SOT457plastic, surface-mounted package (SC-74; TSOP6); 6 leadsPackage information2023-03-03
    REFLOW_BG-BD-1Reflow soldering profileReflow soldering2021-04-06

    支持

    如果您需要设计/技术支持，请告知我们并填写 应答表, 我们会尽快回复您。

    模型

    文件名称标题类型日期
    lvc1g33274LVC1G332 IBIS modelIBIS model2015-09-06

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