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双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74LVC574A-Q100

Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

The 74LVC574A-Q100 is an 8-bit positive-edge triggered D-type flip-flop with 3-state outputs. The device features a clock (CP) and output enable (OE) inputs. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Wide supply voltage range from 1.2 to 3.6 V

  • CMOS low power consumption

  • Direct interface with TTL levels

  • Overvoltage tolerant inputs to 5.5 V

  • High-impedance when VCC = 0 V

  • 8-bit positive edge-triggered register

  • Independent register and 3-state buffer operation

  • Flow-through pin-out architecture

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standard:

    • JESD8-7A (1.65 V to 1.95 V)

    • JESD8-5A (2.3 V to 2.7 V)

    • JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC574ABQ-Q100Production1.2 - 3.6CMOS/LVTTL± 243.2150low-40~125799.550DHVQFN20
74LVC574APW-Q100Production1.2 - 3.6CMOS/LVTTL± 243.2150low-40~1251014.745TSSOP20

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74LVC574ABQ-Q100
DHVQFN20
(SOT764-1) 		SOT764-1SOT764-1_115ActiveLVC574A74LVC574ABQ-Q100X
( 9356 916 07115 )
74LVC574APW-Q100
TSSOP20
(SOT360-1) 		SOT360-1SSOP-TSSOP-VSO-WAVE
SOT360-1_118ActiveLVC574A74LVC574APW-Q100J
( 9356 916 08118 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74LVC574ABQ-Q10074LVC574ABQ-Q100X74LVC574ABQ-Q100
74LVC574APW-Q10074LVC574APW-Q100J74LVC574APW-Q100
品质及可靠性免责声明

文档 (4)

文件名称标题类型日期
74LVC574A_Q100Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-stateData sheet2023-11-02
SOT764-1plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 20 terminals; 0.5 mm pitch; 4.5 mm x 2.5 mm x 1 mm bodyPackage information2022-06-21
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT360-1plastic, thin shrink small outline package; 20 leads; 0.65 mm pitch; 6.5 mm x 4.4 mm x 1.1 mm bodyPackage information2022-06-21

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