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    双极性晶体管

    二极管

    ESD保护、TVS、滤波和信号调节ESD保护

    MOSFET

    氮化镓场效应晶体管(GaN FET)

    绝缘栅双极晶体管(IGBTs)

    模拟和逻辑IC

    汽车应用认证产品(AEC-Q100/Q101)

    74LVC2G00GM

    Dual 2-input NAND gate

    The 74LVC2G00 is a dual 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

    Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

    This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

    此产品已停产

    Features and benefits

    • Wide supply voltage range from 1.65 V to 5.5 V

    • 5 V tolerant outputs for interfacing with 5 V logic

    • High noise immunity

    • ±24 mA output drive (VCC = 3.0 V)

    • CMOS low power dissipation

    • IOFF circuitry provides partial Power-down mode operation

    • Complies with JEDEC standard:

      • JESD8-7 (1.65 V to 1.95 V)

      • JESD8-5 (2.3 V to 2.7 V)

      • JESD8-B/JESD36 (2.7 V to 3.6 V)

    • Latch-up performance exceeds 250 mA

    • Direct interface with TTL levels

    • Overvoltage tolerant inputs to 5.5 V

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    • Multiple package options

    • Specified from -40 °C to +85 °C and -40 °C to +125 °C

    参数类型

    型号 Package name
    74LVC2G00GM XQFN8

    PCB Symbol, Footprint and 3D Model

    Model Name 描述

    封装

    下表中的所有产品型号均已停产 。

    型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
    74LVC2G00GM 74LVC2G00GM,125
    (935277235125)    		 Discontinued / End-of-life V00 SOT902-2
    XQFN8
    (SOT902-2)     		SOT902-2 SOT902-2_125
    74LVC2G00GM,115
    (935277235115)    		 Obsolete V00 暂无信息

    环境信息

    下表中的所有产品型号均已停产 。

    型号 可订购的器件编号 化学成分 RoHS RHF指示符
    74LVC2G00GM 74LVC2G00GM,125 74LVC2G00GM rohs rhf rhf
    74LVC2G00GM 74LVC2G00GM,115 74LVC2G00GM rohs rhf rhf
    品质及可靠性免责声明

    文档 (8)

    文件名称 标题 类型 日期
    74LVC2G00 Dual 2-input NAND gate Data sheet 2024-05-08
    AN10161 PicoGate Logic footprints Application note 2002-10-29
    AN11009 Pin FMEA for LVC family Application note 2019-01-09
    Nexperia_document_guide_MiniLogic_MicroPak_201808 MicroPak leadless logic portfolio guide Brochure 2018-09-03
    lvc2g00 74LVC2G00 IBIS model IBIS model 2014-10-20
    Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
    XQFN8_SOT902-2_mk plastic, extremely thin quad flat package; 8 terminals; 0.55 mm pitch; 1.6 mm x 1.6 mm x 0.5 mm body Marcom graphics 2017-01-28
    SOT902-2 plastic, leadless extremely thin quad flat package; 8 terminals; 0.5 mm pitch; 1.6 mm x 1.6 mm x 0.5 mm body Package information 2020-04-21

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    模型

    文件名称 标题 类型 日期
    lvc2g00 74LVC2G00 IBIS model IBIS model 2014-10-20

    PCB Symbol, Footprint and 3D Model

    Model Name 描述

    How does it work?

    The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.