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    双极性晶体管

    二极管

    ESD保护、TVS、滤波和信号调节ESD保护

    MOSFET

    氮化镓场效应晶体管(GaN FET)

    绝缘栅双极晶体管(IGBTs)

    模拟和逻辑IC

    汽车应用认证产品(AEC-Q100/Q101)

    74LVC823ADB

    9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state

    The 74LVC823A is a 9-bit D-type flip-flop with common clock (pin CP), clock enable (pin CE), master reset (pin MR) and 3-state outputs (pins Qn) for bus-oriented applications. The 9 flip-flops stores the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW to HIGH CP transition, provided pin CE is LOW. When pin CE is HIGH, the flip-flops hold their data. A LOW on pin MR resets all flip-flops. When pin OE is LOW, the contents of the 9 flip-flops are available at the outputs. When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

    Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V applications.

    此产品已停产

    Features and benefits

    • 5 V tolerant inputs/outputs for interfacing with 5 V logic
    • Wide supply voltage range from 1.2 V to 3.6 V
    • CMOS low power consumption
    • Direct interface with TTL levels
    • Flow-through pinout architecture
    • 9-bit positive edge-triggered register
    • Independent register and 3-state buffer operation
    • Complies with JEDEC standard:
      • JESD8-7A (1.65 V to 1.95 V)
      • JESD8-5A (2.3 V to 2.7 V)
      • JESD8-C/JESD36 (2.7 V to 3.6 V)
    • ESD protection:
      • HBM JESD22-A114F exceeds 2000 V
      • MM JESD22-A115-B exceeds 200 V
      • CDM JESD22-C101E exceeds 1000 V
    • Specified from -40 °C to +85 °C and -40 °C to +125 °C.

    参数类型

    型号 Package name
    74LVC823ADB SSOP24

    封装

    下表中的所有产品型号均已停产 。

    型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
    74LVC823ADB 74LVC823ADB,112
    (935262540112)    		 Obsolete LVC823A Standard Procedure Standard Procedure SOT340-1
    SSOP24
    (SOT340-1)     		SOT340-1 SSOP-TSSOP-VSO-REFLOW
    SSOP-TSSOP-VSO-WAVE
    		暂无信息
    74LVC823ADB,118
    (935262540118)    		 Obsolete LVC823A Standard Procedure Standard Procedure SOT340-1_118

    环境信息

    下表中的所有产品型号均已停产 。

    型号 可订购的器件编号 化学成分 RoHS RHF指示符
    74LVC823ADB 74LVC823ADB,112 74LVC823ADB rohs rhf rhf
    74LVC823ADB 74LVC823ADB,118 74LVC823ADB rohs rhf rhf
    品质及可靠性免责声明

    文档 (9)

    文件名称 标题 类型 日期
    74LVC823A 9-bit D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state Data sheet 2020-06-19
    AN11009 Pin FMEA for LVC family Application note 2019-01-09
    AN263 Power considerations when using CMOS and BiCMOS logic devices Application note 2023-02-07
    lvc823a lvc823a IBIS model IBIS model 2013-04-09
    Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
    SOT340-1 plastic, shrink small outline package; 24 leads; 0.65 mm pitch; 8.2 mm x 5.3 mm x 2 mm body Package information 2020-04-21
    SSOP-TSSOP-VSO-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
    lvc lvc Spice model SPICE model 2013-05-07
    SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

    支持

    如果您需要设计/技术支持，请告知我们并填写 应答表 我们会尽快回复您。

    模型

    文件名称 标题 类型 日期
    lvc823a lvc823a IBIS model IBIS model 2013-04-09
    lvc lvc Spice model SPICE model 2013-05-07

    How does it work?

    The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.