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双极性晶体管

二极管

ESD保护、TVS、滤波和信号调节ESD保护

MOSFET

氮化镓场效应晶体管(GaN FET)

绝缘栅双极晶体管(IGBTs)

模拟和逻辑IC

汽车应用认证产品(AEC-Q100/Q101)

74ALVT16821DL

20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state

The 74ALVT16821 is a 20-bit positive-edge triggered D-type flip-flop with 3-state outputs.

The device can be used as two 10-bit flip-flops or one 20-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 10-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops. Bus hold data inputs eliminate the need for external pull-up resistors to define unused inputs

此产品已停产

Features and benefits

  • Wide supply voltage range from 2.3 V to 3.6 V

  • Overvoltage tolerant inputs to 5.5 V

  • 20-bit positive-edge triggered register

  • BiCMOS high speed and output drive

  • Direct interface with TTL levels

  • Bus hold on data inputs

  • No bus current loading when output is tied to 5 V bus

  • Power-up 3-state

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to 85 °C

参数类型

型号 Package name
74ALVT16821DL SSOP56

封装

下表中的所有产品型号均已停产 。

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74ALVT16821DL 74ALVT16821DL,112
(935210000112)		 Obsolete ALVT16821 Standard Procedure Standard Procedure SOT371-1
SSOP56
(SOT371-1) 		SOT371-1 SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE
暂无信息
74ALVT16821DL,118
(935210000118)		 Obsolete ALVT16821 Standard Procedure Standard Procedure 暂无信息
74ALVT16821DL,512
(935210000512)		 Obsolete ALVT16821 Standard Procedure Standard Procedure 暂无信息
74ALVT16821DL,518
(935210000518)		 Obsolete ALVT16821 Standard Procedure Standard Procedure 暂无信息

环境信息

下表中的所有产品型号均已停产 。

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74ALVT16821DL 74ALVT16821DL,112 74ALVT16821DL rhf
74ALVT16821DL 74ALVT16821DL,118 74ALVT16821DL rhf
74ALVT16821DL 74ALVT16821DL,512 74ALVT16821DL rohs rhf rhf
74ALVT16821DL 74ALVT16821DL,518 74ALVT16821DL rohs rhf rhf
品质及可靠性免责声明

文档 (7)

文件名称 标题 类型 日期
74ALVT16821 20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state Data sheet 2024-06-25
alvt16821 alvt16821 IBIS model IBIS model 2013-04-08
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT371-1 plastic, shrink small outline package; 56 leads; 0.635 mm pitch; 18.45 mm x 7.5 mm x 2.8 mm body Package information 2020-04-21
SSOP-TSSOP-VSO-REFLOW Footprint for reflow soldering Reflow soldering 2009-10-08
alvt16 alvt16 Spice model SPICE model 2013-05-07
SSOP-TSSOP-VSO-WAVE Footprint for wave soldering Wave soldering 2009-10-08

支持

如果您需要设计/技术支持，请告知我们并填写 应答表 我们会尽快回复您。

模型

文件名称 标题 类型 日期
alvt16821 alvt16821 IBIS model IBIS model 2013-04-08
alvt16 alvt16 Spice model SPICE model 2013-05-07

How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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