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74LVC2G00-Q100

Dual 2-input NAND gate

The 74LVC2G00-Q100 is a dual 2-input NAND gate. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Wide supply voltage range from 1.65 V to 5.5 V

  • 5 V tolerant outputs for interfacing with 5 V logic

  • High noise immunity

  • ±24 mA output drive (VCC = 3.0 V)

  • CMOS low power dissipation

  • IOFF circuitry provides partial Power-down mode operation

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8-B/JESD36 (2.7 V to 3.6 V)

  • Latch-up performance exceeds 250 mA

  • Direct interface with TTL levels

  • Overvoltage tolerant inputs to 5.5 V

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC2G00DC-Q100Production1.65 - 5.5CMOS/LVTTL± 322.21752low-40~12520032.4110VSSOP8

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74LVC2G00DC-Q100
VSSOP8
(SOT765-1) 		SOT765-1SOT765-1_125ActiveV0074LVC2G00DC-Q100H
( 9353 072 78125 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74LVC2G00DC-Q10074LVC2G00DC-Q100H74LVC2G00DC-Q100Always Pb-free
品质及可靠性免责声明

文档 (6)

文件名称标题类型日期
74LVC2G00_Q100Dual 2-input NAND gateData sheet2023-08-14
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc2g0074LVC2G00 IBIS modelIBIS model2014-10-20
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
SOT765-1plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm bodyPackage information2022-06-03

支持

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模型

文件名称标题类型日期
lvc2g0074LVC2G00 IBIS modelIBIS model2014-10-20

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