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74LVC74A-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

The 74LVC74A-Q100 is a dual edge triggered D-type flip-flop with individual data (nD) inputs, clock (nCP) inputs, set (nSD) and (nRD) inputs, and complementary nQ and nQ outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the nQ output on the LOW-to-HIGH transition of the clock pulse. The nD inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • 5 V tolerant inputs for interlacing with 5 V logic

  • Wide supply voltage range from 1.2 V to 3.6 V

  • CMOS low power consumption

  • Direct interface with TTL levels

  • Complies with JEDEC standard:

    • JESD8-7A (1.65 V to 1.95 V)

    • JESD8-5A (2.3 V to 2.7 V)

    • JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • DHVQFN package with Side-Wettable Flanks enabling Automatic Optical Inspection (AOI) of solder joints

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC74ABQ-Q100Production1.2 - 3.6CMOS/LVTTL± 242.5250low-40~12510721.775DHVQFN14
74LVC74AD-Q100Production1.2 - 3.6CMOS/LVTTL± 242.5250low-40~12510921.068SO14
74LVC74APW-Q100Production1.2 - 3.6CMOS/LVTTL± 242.5250low-40~1251428.168TSSOP14

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74LVC74ABQ-Q100
DHVQFN14
(SOT762-1) 		SOT762-1SOT762-1_115ActiveVC74A74LVC74ABQ-Q100X
( 9353 013 68115 )
74LVC74AD-Q100
SO14
(SOT108-1) 		SOT108-1SO-SOJ-REFLOW
SO-SOJ-WAVE
SOT108-1_118Active74LVC74AD74LVC74AD-Q100J
( 9353 004 63118 )
74LVC74APW-Q100
TSSOP14
(SOT402-1) 		SOT402-1SSOP-TSSOP-VSO-WAVE
SOT402-1_118ActiveLVC74A74LVC74APW-Q100J
( 9353 004 64118 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74LVC74ABQ-Q10074LVC74ABQ-Q100X74LVC74ABQ-Q100Always Pb-free
74LVC74AD-Q10074LVC74AD-Q100J74LVC74AD-Q100Always Pb-free
74LVC74APW-Q10074LVC74APW-Q100J74LVC74APW-Q100Always Pb-free
品质及可靠性免责声明

文档 (13)

文件名称标题类型日期
74LVC74A_Q100Dual D-type flip-flop with set and reset; positive-edge triggerData sheet2024-02-22
AN263Power considerations when using CMOS and BiCMOS logic devicesApplication note2023-02-07
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc74alvc74a IBIS modelIBIS model2013-04-07
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
lvclvc Spice modelSPICE model2013-05-06
SOT762-1plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 14 terminals; 0.5 mm pitch; 2.5 x 3 x 1 mm bodyPackage information2023-04-05
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT402-1plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm bodyPackage information2023-11-07
SO-SOJ-WAVEFootprint for wave solderingWave soldering2009-10-08
SO-SOJ-REFLOWFootprint for reflow solderingReflow soldering2009-10-08
WAVE_BG-BD-1Wave soldering profileWave soldering2021-09-08
SOT108-1plastic, small outline package; 14 leads; 1.27 mm pitch; 8.65 mm x 3.9 mm x 1.75 mm bodyPackage information2023-11-07

支持

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模型

文件名称标题类型日期
lvc74alvc74a IBIS modelIBIS model2013-04-07
lvclvc Spice modelSPICE model2013-05-06

样品

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