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    74LVC16374A-Q100; 74LVCH16374A-Q100

    16-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state

    The 74LVC16374A-Q100; 74LVCH16374A-Q100 is a 16-bit edge-triggered D-type flip-flop with 3-state outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. The device features two clocks (1CP and 2CP) and two output enables (1OE and 2OE), each controlling 8-bits. The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (nCP) transition. A HIGH on nOE causes the outputs to assume a high-impedance OFF-state. Operation of the nOE input does not affect the state of the flip-flops . Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

    Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

    This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

    This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

    特性

    • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

      • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

    • Overvoltage tolerant inputs to 5.5 V

    • Wide supply voltage range from 1.2 V to 3.6 V

    • CMOS low power dissipation

    • Multibyte flow-through standard pinout architecture

    • Low inductance multiple supply pins for minimum noise and ground bounce

    • Direct interface with TTL levels

    • All data inputs have bus hold (74LVCH16374A-Q100 only)

    • High-impedance outputs when VCC = 0 V

    • Complies with JEDEC standard:

      • JESD8-7A (1.65 V to 1.95 V)

      • JESD8-5A (2.3 V to 2.7 V)

      • JESD8-C/JESD36 (2.7 V to 3.6 V)

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    参数类型

    Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
    74LVC16374ADGG-Q100Production1.2 - 3.6CMOS/LVTTL± 243.8150low-40~125822.037TSSOP48
    74LVCH16374ADGG-Q100Production1.2 - 3.6CMOS/LVTTL± 243.8150low-40~125822.037TSSOP48

    封装

    型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
    74LVC16374ADGG-Q100
    TSSOP48
    (SOT362-1)     		SOT362-1SSOP-TSSOP-VSO-WAVE
    		SOT362-1_118ActiveLVC16374A74LVC16374ADGG-Q1J
    ( 9353 002 32118 )
    74LVCH16374ADGG-Q100
    TSSOP48
    (SOT362-1)     		SOT362-1SSOP-TSSOP-VSO-WAVE
    		SOT362-1_118ActiveLVCH16374A74LVCH16374ADGG-QJ
    ( 9353 003 57118 )

    环境信息

    型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
    74LVC16374ADGG-Q10074LVC16374ADGG-Q1J74LVC16374ADGG-Q100Always Pb-free
    74LVCH16374ADGG-Q10074LVCH16374ADGG-QJ74LVCH16374ADGG-Q100Always Pb-free
    品质及可靠性免责声明

    文档 (7)

    文件名称标题类型日期
    74LVC_LVCH16374A_Q10016-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-stateData sheet2024-04-22
    AN263Power considerations when using CMOS and BiCMOS logic devicesApplication note2023-02-07
    AN11009Pin FMEA for LVC familyApplication note2019-01-09
    lvch16374alvch16374a IBIS modelIBIS model2013-04-07
    lvc16374alvc16374a IBIS modelIBIS model2013-04-07
    SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
    SOT362-1plastic thin shrink small outline package; 48 leads; body width 6.1 mmPackage information2024-01-05

    支持

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    模型

    文件名称标题类型日期
    lvch16374alvch16374a IBIS modelIBIS model2013-04-07
    lvc16374alvc16374a IBIS modelIBIS model2013-04-07

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