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74HC109-Q100; 74HCT109-Q100

Dual JK flip-flop with set and reset; positive-edge-trigger

The 74HC109-Q100; 74HCT109-Q100 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by connecting the J and K inputs together. This device features reduced input threshold levels to allow interfacing to TTL logic levels. Inputs also include clamp diodes, this enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • J and K inputs for easy D-type flip-flop

  • Toggle flip-flop or "do nothing" mode

  • Wide supply voltage range:

    • For 74HC109-Q100: from 2.0 V to 6.0 V

    • For 74HCT109-Q100: from 4.5 V to 5.5 V

  • CMOS low power dissipation

  • High noise immunity

  • Input levels:

    • For 74HC109-Q100: CMOS level

    • For 74HCT109-Q100: TTL level

  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

  • 74HC109-Q100 complies with JEDEC standards:

    • JESD8C (2.7 V to 3.6 V)

    • JESD7A (2.0 V to 6.0 V)

  • 74HCT109-Q100 complies with JEDEC standard JESD7A (2.0 V to 6.0 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74HC109D-Q100Production2.0 - 6.0CMOS± 5.21575low-40~125866.644SO16
74HCT109D-Q100Production4.5 - 5.5TTL± 41761low-40~125866.644SO16
74HCT109PW-Q100Production4.5 - 5.5TTL± 41761low-40~1251193.248.1TSSOP16

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号,(订购码(12NC))
74HC109D-Q100
SO16
(SOT109-1)
SOT109-1SO-SOJ-REFLOW
SO-SOJ-WAVE
SOT109-1_118Active74HC109D74HC109D-Q100J
( 9353 342 21118 )
74HCT109D-Q100
SO16
(SOT109-1)
SOT109-1SO-SOJ-REFLOW
SO-SOJ-WAVE
SOT109-1_118Active74HCT109D74HCT109D-Q100J
( 9353 327 77118 )
74HCT109PW-Q100
TSSOP16
(SOT403-1)
SOT403-1SSOP-TSSOP-VSO-WAVE
SOT403-1_118ActiveHCT10974HCT109PW-Q100J
( 9353 364 88118 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74HC109D-Q10074HC109D-Q100J74HC109D-Q100week 25, 2019
74HCT109D-Q10074HCT109D-Q100J74HCT109D-Q100week 25, 2019
74HCT109PW-Q10074HCT109PW-Q100J74HCT109PW-Q100week 25, 2019
品质及可靠性免责声明

文档 (9)

文件名称标题类型日期
74HC_HCT109_Q100Dual JK flip-flop with set and reset; positive-edge-triggerData sheet2024-02-21
AN11044Pin FMEA 74HC/74HCT familyApplication note2019-01-09
HCT_USER_GUIDEHC/T User GuideUser manual1997-10-31
SO-SOJ-WAVEFootprint for wave solderingWave soldering2009-10-08
SO-SOJ-REFLOWFootprint for reflow solderingReflow soldering2009-10-08
WAVE_BG-BD-1Wave soldering profileWave soldering2021-09-08
SOT109-1plastic, small outline package; 16 leads; 1.27 mm pitch; 9.9 mm x 3.9 mm x 1.75 mm bodyPackage information2023-11-07
SOT403-1plastic, thin shrink small outline package; 16 leads; 5 mm x 4.4 mm x 1.2 mm bodyPackage information2023-11-08
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08

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