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74AUP2G80DC-Q100

Low-power dual D-type flip-flop; positive-edge trigger

Automotive qualified

The 74AUP2G80-Q100 provides the dual positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one setup time prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire V_CC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire V_CC range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF circuitry disables the output, preventing a damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

Automotive product qualification in accordance with AEC-Q100 (Grade 1)
- Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range from 0.8 V to 3.6 V
High noise immunity
Low static power consumption; I_CC = 0.9 μA (maximum)
Latch-up performance exceeds 100 mA per JESD78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V_CC
I_OFF circuitry provides partial Power-down mode operation
Complies with JEDEC standards:
- JESD8-12 (0.8 V to 1.3 V)
- JESD8-11 (0.9 V to 1.65 V)
- JESD8-7 (1.2 V to 1.95 V)
- JESD8-5 (1.8 V to 2.7 V)
- JESD8-B (2.7 V to 3.6 V)
ESD protection:
- HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V
- CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

参数类型

型号	Product status	V_CC (V)	Logic switching levels	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Power dissipation considerations	T_amb (°C)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name
74AUP2G80DC-Q100	Production	0.8 - 3.6	CMOS	± 1.9	9.1	400	ultra low	-40~125	203	34.1	113	VSSOP8

封装

型号	可订购的器件编号，（订购码(12NC)）	状态	标示	封装	外形图	回流焊/波峰焊	包装
74AUP2G80DC-Q100	74AUP2G80DC-Q100H (935691578125)	Active	p80	VSSOP8 (SOT765-1)	SOT765-1		SOT765-1_125

环境信息

型号	可订购的器件编号	化学成分	RoHS	RHF指示符
74AUP2G80DC-Q100	74AUP2G80DC-Q100H	74AUP2G80DC-Q100

品质及可靠性免责声明

Series

文档 (7)

文件名称	标题	类型	日期
74AUP2G80_Q100	Low-power dual D-type flip-flop; positive-edge trigger	Data sheet	2023-10-16
Nexperia_document_guide_MiniLogic_PicoGate_201901	PicoGate leaded logic portfolio guide	Brochure	2019-01-07
SOT765-1	3D model for products with SOT765-1 package	Design support	2020-01-22
Nexperia_package_poster	Nexperia package poster	Leaflet	2020-05-15
VSSOP8_SOT765-1_mk	plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body	Marcom graphics	2017-01-28
SOT765-1	plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm body	Package information	2022-06-03
SOT765-1_125	VSSOP8; Reel pack for SMD, 7''; Q3/T4 product orientation	Packing information	2020-04-21

支持

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模型

文件名称	标题	类型	日期
SOT765-1	3D model for products with SOT765-1 package	Design support	2020-01-22

订购、定价与供货

型号	Orderable part number	Ordering code (12NC)	状态	包装	Packing Quantity	在线购买
74AUP2G80DC-Q100	74AUP2G80DC-Q100H	935691578125	Active	SOT765-1_125	3,000	订单产品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

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