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74LVC3G07DP-Q100

Triple buffer with open-drain output

The 74LVC3G07-Q100 provides three non-inverting buffers.

The output of the device is an open-drain and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall time.

This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

Features and benefits

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Wide supply voltage range from 1.65 V to 5.5 V

  • 5 V tolerant input/output for interfacing with 5 V logic

  • High noise immunity

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8-B/JESD36 (2.7 V to 3.6 V).

  • -24 mA output drive (VCC = 3.0 V)

  • CMOS low power consumption

  • Latch-up performance exceeds 250 mA

  • Direct interface with TTL levels

  • Inputs accept voltages up to 5 V

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

参数类型

型号 Product status VCC (V) Logic switching levels Output drive capability (mA) fmax (MHz) Nr of bits Power dissipation considerations Tamb (°C) Rth(j-a) (K/W) Ψth(j-top) (K/W) Rth(j-c) (K/W) Package name
74LVC3G07DP-Q100 Production 1.65 - 5.5 CMOS/LVTTL 32 175 3 low -40~125 217 20.7 106 TSSOP8

PCB Symbol, Footprint and 3D Model

Model Name 描述

封装

型号 可订购的器件编号，（订购码(12NC)） 状态 标示 封装 外形图 回流焊/波峰焊 包装
74LVC3G07DP-Q100 74LVC3G07DP-Q100H
(935300249125)		 Active V07 SOT505-2
TSSOP8
(SOT505-2) 		SOT505-2 SOT505-2_125

环境信息

型号 可订购的器件编号 化学成分 RoHS RHF指示符
74LVC3G07DP-Q100 74LVC3G07DP-Q100H 74LVC3G07DP-Q100 rohs rhf rhf
品质及可靠性免责声明

文档 (8)

文件名称 标题 类型 日期
74LVC3G07_Q100 Triple buffer with open-drain output Data sheet 2023-08-24
Nexperia_document_guide_MiniLogic_PicoGate_201901 PicoGate leaded logic portfolio guide Brochure 2019-01-07
SOT505-2 3D model for products with SOT505-2 package Design support 2019-01-18
lvc3g07 74LVC3G07 IBIS model IBIS model 2015-01-15
Nexperia_package_poster Nexperia package poster Leaflet 2020-05-15
SOT505-2 plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm body Package information 2022-06-03
SOT505-2_125 TSSOP8; Reel pack for SMD, 7''; Q3/T4 product orientation Packing information 2020-04-21
74LVC3G07DP-Q100_Nexperia_Product_Reliability 74LVC3G07DP-Q100 Nexperia Product Reliability Quality document 2023-05-29

支持

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模型

文件名称 标题 类型 日期
lvc3g07 74LVC3G07 IBIS model IBIS model 2015-01-15
SOT505-2 3D model for products with SOT505-2 package Design support 2019-01-18

PCB Symbol, Footprint and 3D Model

Model Name 描述

订购、定价与供货

型号 Orderable part number Ordering code (12NC) 状态 包装 Packing Quantity 在线购买
74LVC3G07DP-Q100 74LVC3G07DP-Q100H 935300249125 Active SOT505-2_125 3,000 订单产品

样品

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How does it work?

The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.

可订购部件

型号 可订购的器件编号 订购代码(12NC) 封装 从经销商处购买
74LVC3G07DP-Q100 74LVC3G07DP-Q100H 935300249125 SOT505-2 订单产品
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