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74LVC2G38



Dual 2-input NAND gate; open drain




The 74LVC2G38 is a dual 2-input NAND gate with open-drain outputs. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.


This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.














特性


    

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    Wide supply voltage range from 1.65 V to 5.5 V
    

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    5 V tolerant outputs for interfacing with 5 V logic
    

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  • 

    Overvoltage tolerant inputs to 5.5 V
    

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  • 

    High noise immunity
    

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  • 

    CMOS low power dissipation
    

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  • 

    IOFF circuitry provides partial Power-down mode operation
    

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  • 

    ±24 mA output drive (VCC = 3.0 V)
    

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    Open-drain outputs
    

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    Latch-up performance exceeds 250 mA
    

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  • 

    Direct interface with TTL levels
    

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  • 

    Complies with JEDEC standard:
    

      

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      JESD8-7 (1.65 V to 1.95 V)
      

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    • 

      JESD8-5 (2.3 V to 2.7 V)
      

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      JESD8C (2.7 V to 3.6 V)
      

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      JESD36 (4.5 V to 5.5 V)
      

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    • 

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    ESD protection:
    

      

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      HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
      

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      CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
      

      • 

    

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    Multiple package options
    

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    Specified from -40 °C to +85 °C and -40 °C to +125 °C
    

    • 





参数类型
Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC2G38DCProduction1.65 - 5.5CMOS/LVTTL322.11752low-40~12520032.4110VSSOP8
74LVC2G38DPProduction1.65 - 5.5CMOS/LVTTL322.11752low-40~12521018.8104TSSOP8
74LVC2G38GNProduction1.65 - 5.5CMOS/LVTTL322.11752low-40~1252319.5142XSON8
74LVC2G38GSProduction1.65 - 5.5CMOS/LVTTL322.11752low-40~1252699.7141XSON8
74LVC2G38GTProduction1.65 - 5.5CMOS/LVTTL322.11752low-40~1253175.6150XSON8
74LVC2G38GXProduction1.65 - 5.5CMOS/LVTTL322.11752low-40~125---X2SON8
封装
型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74LVC2G38DC
VSSOP8

(SOT765-1)
SOT765-1SOT765-1_125ActiveY3874LVC2G38DC,125
(
9352 735 84125
)

74LVC2G38DP
TSSOP8

(SOT505-2)
SOT505-2SOT505-2_125ActiveY3874LVC2G38DP,125
(
9352 745 79125
)

74LVC2G38GN
XSON8

(SOT1116)
SOT1116REFLOW_BG-BD-1
SOT1116_115ActiveYB74LVC2G38GN,115
(
9352 922 45115
)

74LVC2G38GS
XSON8

(SOT1203)
SOT1203REFLOW_BG-BD-1
SOT1203_115ActiveYB74LVC2G38GS,115
(
9352 923 85115
)

74LVC2G38GT
XSON8

(SOT833-1)
SOT833-1SOT833-1_115ActiveY3874LVC2G38GT,115
(
9352 789 23115
)

74LVC2G38GX
X2SON8

(SOT1233-2)
SOT1233-2SOT1233-2_115ActiveYB74LVC2G38GXX
(
9353 397 99115
)

环境信息
型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74LVC2G38DC74LVC2G38DC,12574LVC2G38DCweek 1, 2005
74LVC2G38DP74LVC2G38DP,12574LVC2G38DPweek 41, 2004
74LVC2G38GN74LVC2G38GN,11574LVC2G38GNAlways Pb-free
74LVC2G38GS74LVC2G38GS,11574LVC2G38GSAlways Pb-free
74LVC2G38GT74LVC2G38GT,11574LVC2G38GTAlways Pb-free
74LVC2G38GX74LVC2G38GXX74LVC2G38GXweek 25, 2019
品质及可靠性免责声明
文档 (17)
文件名称标题类型日期
74LVC2G38Dual 2-input NAND gate; open drainData sheet2024-04-30
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc2g3874LVC2G38 IBIS modelIBIS model2014-10-20
Nexperia_document_leaflet_Logic_X2SON_packages_062018X2SON ultra-small 4, 5, 6 & 8-pin leadless packagesLeaflet2018-06-05
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
SOT1233-2plastic thermal enhanced extremely thin small outline package; no leads;8 terminals; body 1.35 x 0.8 x 0.32 mmPackage information2022-04-21
SOT505-2plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm bodyPackage information2022-06-03
MAR_SOT1203MAR_SOT1203 TopmarkTop marking2013-06-03
SOT1203plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm bodyPackage information2022-06-03
REFLOW_BG-BD-1Reflow soldering profileReflow soldering2021-04-06
MAR_SOT833MAR_SOT833 TopmarkTop marking2013-06-03
SOT833-1plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm bodyPackage information2022-06-03
SOT765-1plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm bodyPackage information2022-06-03
MAR_SOT1116MAR_SOT1116 TopmarkTop marking2013-06-03
SOT1116plastic, leadless extremely thin small outline package; 8 terminals; 0.3 mm pitch; 1.2 mm x 1 mm x 0.35 mm bodyPackage information2022-06-02
REFLOW_BG-BD-1Reflow soldering profileReflow soldering2021-04-06
支持
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模型
文件名称标题类型日期
lvc2g3874LVC2G38 IBIS modelIBIS model2014-10-20
样品
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