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74AUP2G97

Low-power dual PCB configurable multiple function gate

The 74AUP2G97 is a dual configurable multiple function gate with Schmitt-trigger inputs. Each gate within the device can be configured as any of the following logic functions MUX, AND, OR, NAND, NOR, inverter and buffer; using the 3-bit input. All inputs can be connected directly to VCC or GND.

This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

特性

  • Wide supply voltage range from 0.8 V to 3.6 V
  • High noise immunity
  • ESD protection:
    • HBM JESD22-A114F exceeds 5000 V
    • MM JESD22-A115-A exceeds 200 V
    • CDM JESD22-C101E exceeds 1000 V
  • Low static power consumption; ICC = 0.9 μA (maximum)
  • Latch-up performance exceeds 100 mA per JESD 78 Class II
  • Inputs accept voltages up to 3.6 V
  • Low noise overshoot and undershoot < 10 % of VCC
  • IOFF circuitry provides partial power-down mode operation
  • Multiple package options
  • Specified from ‑40 °C to +85 °C and ‑40 °C to +125 °C

参数类型

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Package name
74AUP2G97DPProductionn.a.n.a.CMOS± 1.98.7702ultra low-40~12512030.0TSSOP10
74AUP2G97GUProductionn.a.n.a.CMOS± 1.98.7702ultra low-40~12514248.0XQFN10

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74AUP2G97DP
TSSOP10
(SOT552-1) 		SOT552-1SSOP-TSSOP-VSO-WAVE
SOT552-1_118ActiveaV74AUP2G97DPJ
( 9353 044 81118 )
74AUP2G97GU
XQFN10
(SOT1160-1) 		SOT1160-1SOT1160-1_115ActiveaV74AUP2G97GUX
( 9353 044 84115 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74AUP2G97DP74AUP2G97DPJ74AUP2G97DPAlways Pb-free
74AUP2G97GU74AUP2G97GUX74AUP2G97GUAlways Pb-free
品质及可靠性免责声明

文档 (6)

文件名称标题类型日期
74AUP2G97Low-power dual PCB configurable multiple function gateData sheet2023-08-01
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
SOT552-1plastic, thin shrink small outline package; 10 leads; 0.5 mm pitch; 3 mm x 3 mm x 1.1 mm bodyPackage information2022-06-07
SOT1160-1plastic, leadless extremely thin quad flat package; 10 terminals; 0.4 mm pitch; 1.4 mm x 1.8 mm x 0.5 mm bodyPackage information2022-06-07

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样品

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