NG体育娱乐，ng体育平台

×

74AUP2G240

Low-power dual inverting buffer/line driver; 3-state

The 74AUP2G240 provides the dual inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (nOE). A HIGH level at pin nOE causes the output to assume a high-impedance OFF-state.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

This device has the input-disable feature, which allows floating input signals. The inputs are disabled when the output enable input nOE is HIGH.

特性

  • Wide supply voltage range from 0.8 V to 3.6 V

  • High noise immunity

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • Low static power consumption; ICC = 0.9 μA (maximum)

  • Latch-up performance exceeds 100 mA per JESD78 Class II

  • Inputs accept voltages up to 3.6 V

  • Low-noise overshoot and undershoot < 10 % of VCC

  • Input-disable feature allows floating input conditions

  • IOFF circuitry provides partial Power-down mode operation

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)fmax (MHz)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Rth(j-c) (K/W)Package name
74AUP2G240DCProduction0.8 - 3.6CMOS± 1.9702ultra low-40~125203113VSSOP8
74AUP2G240GNProduction0.8 - 3.6CMOS± 1.9702ultra low-40~125238148XSON8
74AUP2G240GSProduction0.8 - 3.6CMOS± 1.9702ultra low-40~125276146XSON8
74AUP2G240GTProduction0.8 - 3.6CMOS± 1.9702ultra low-40~125327157XSON8

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74AUP2G240DC
VSSOP8
(SOT765-1) 		SOT765-1SOT765-1_125Activep4074AUP2G240DC,125
( 9352 807 36125 )
74AUP2G240GN
XSON8
(SOT1116) 		SOT1116REFLOW_BG-BD-1
SOT1116_115Activep274AUP2G240GN,115
( 9352 922 24115 )
74AUP2G240GS
XSON8
(SOT1203) 		SOT1203REFLOW_BG-BD-1
SOT1203_115Activep274AUP2G240GS,115
( 9352 927 84115 )
74AUP2G240GT
XSON8
(SOT833-1) 		SOT833-1SOT833-1_115Activep4074AUP2G240GT,115
( 9352 807 37115 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74AUP2G240DC74AUP2G240DC,12574AUP2G240DCAlways Pb-free
74AUP2G240GN74AUP2G240GN,11574AUP2G240GNAlways Pb-free
74AUP2G240GS74AUP2G240GS,11574AUP2G240GSAlways Pb-free
74AUP2G240GT74AUP2G240GT,11574AUP2G240GTAlways Pb-free
品质及可靠性免责声明

文档 (15)

文件名称标题类型日期
74AUP2G240Low-power dual inverting buffer/line driver; 3-stateData sheet2023-07-27
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11052Pin FMEA for AUP familyApplication note2019-01-09
aup2g240aup2g240 IBIS modelIBIS model2013-04-07
Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
MAR_SOT1203MAR_SOT1203 TopmarkTop marking2013-06-03
SOT1203plastic, leadless extremely thin small outline package; 8 terminals; 0.35 mm pitch; 1.35 mm x 1 mm x 0.35 mm bodyPackage information2022-06-03
REFLOW_BG-BD-1Reflow soldering profileReflow soldering2021-04-06
MAR_SOT833MAR_SOT833 TopmarkTop marking2013-06-03
SOT833-1plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm bodyPackage information2022-06-03
SOT765-1plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm bodyPackage information2022-06-03
MAR_SOT1116MAR_SOT1116 TopmarkTop marking2013-06-03
SOT1116plastic, leadless extremely thin small outline package; 8 terminals; 0.3 mm pitch; 1.2 mm x 1 mm x 0.35 mm bodyPackage information2022-06-02
REFLOW_BG-BD-1Reflow soldering profileReflow soldering2021-04-06

支持

如果您需要设计/技术支持，请告知我们并填写 应答表, 我们会尽快回复您。

模型

文件名称标题类型日期
aup2g240aup2g240 IBIS modelIBIS model2013-04-07

样品

安世半导体客户可通过我们的销售机构或直接通过在线样品商店订购样品： https://extranet.nexperia.com.

样品订单通常需要2-4天寄送时间。

如果您尚未取得安世半导体的直接采购帐号，我们的全球与区域经销网络可以协助您取得样品

NG体育娱乐，ng体育平台