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74LVC1G74-Q100

Single D-type flip-flop with set and reset; positive edge trigger

The 74LVC1G74-Q100 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), set (SD) and reset (RD) inputs, and complementary Q and Q outputs. Data at the D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments.

Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.

This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Wide supply voltage range from 1.65 V to 5.5 V

  • Overvoltage tolerant inputs to 5.5 V

  • High noise immunity

  • ±24 mA output drive (VCC = 3.0 V)

  • CMOS low power consumption

  • Direct interface with TTL levels

  • IOFF circuitry provides partial Power-down mode operation

  • Latch-up performance exceeds 250 mA

  • Complies with JEDEC standard:

    • JESD8-7 (1.65 V to 1.95 V)

    • JESD8-5 (2.3 V to 2.7 V)

    • JESD8-B/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Multiple package options

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVC1G74DC-Q100Production1.65 - 5.5CMOS/LVTTL± 323.5280low-40~12520636.4117VSSOP8
74LVC1G74DP-Q100Production1.65 - 5.5CMOS/LVTTL± 323.5280low-40~12522021.3107TSSOP8
74LVC1G74GT-Q100Production1.65 - 5.5CMOS/LVTTL± 323.5280low-40~1253396.8166XSON8

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74LVC1G74DC-Q100
VSSOP8
(SOT765-1) 		SOT765-1SOT765-1_125ActiveV7474LVC1G74DC-Q100H
( 9352 992 93125 )
74LVC1G74DP-Q100
TSSOP8
(SOT505-2) 		SOT505-2SOT505-2_125ActiveV7474LVC1G74DP-Q100H
( 9352 992 94125 )
74LVC1G74GT-Q100
XSON8
(SOT833-1) 		SOT833-1SOT833-1_115ActiveV7474LVC1G74GT-Q100X
( 9352 992 97115 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74LVC1G74DC-Q10074LVC1G74DC-Q100H74LVC1G74DC-Q100Always Pb-free
74LVC1G74DP-Q10074LVC1G74DP-Q100H74LVC1G74DP-Q100Always Pb-free
74LVC1G74GT-Q10074LVC1G74GT-Q100X74LVC1G74GT-Q100Always Pb-free
品质及可靠性免责声明

文档 (9)

文件名称标题类型日期
74LVC1G74_Q100Single D-type flip-flop with set and reset; positive edge triggerData sheet2023-08-18
AN10161PicoGate Logic footprintsApplication note2002-10-29
AN11009Pin FMEA for LVC familyApplication note2019-01-09
lvc1g7474LVC1G74 IBIS modelIBIS model2014-10-20
Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
SOT505-2plastic, thin shrink small outline package; 8 leads; 0.65 mm pitch; 3 mm x 3 mm x 1.1 mm bodyPackage information2022-06-03
MAR_SOT833MAR_SOT833 TopmarkTop marking2013-06-03
SOT833-1plastic, leadless extremely thin small outline package; 8 terminals; 0.5 mm pitch; 1 mm x 1.95 mm x 0.5 mm bodyPackage information2022-06-03
SOT765-1plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm bodyPackage information2022-06-03

支持

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模型

文件名称标题类型日期
lvc1g7474LVC1G74 IBIS modelIBIS model2014-10-20

样品

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