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    74AUP1G175-Q100

    Low-power D-type flip-flop with reset; positive-edge trigger

    The 74AUP1G175 is a single positive edge triggered D-type flip-flop with individual data (D), clock (CP), master reset (MR) inputs, and Q output. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition will be stored in the flip-flop and appear at the Q output. A LOW on MR causes the flip-flop and output to be reset to LOW. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device ensures very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down.

    This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

    特性

    • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

      • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

    • Wide supply voltage range from 0.8 V to 3.6 V

    • CMOS low power dissipation

    • High noise immunity

    • Complies with JEDEC standards:

      • JESD8-12 (0.8 V to 1.3 V)

      • JESD8-11 (0.9 V to 1.65 V)

      • JESD8-7 (1.2 V to 1.95 V)

      • JESD8-5 (1.8 V to 2.7 V)

      • JESD8C (2.7 V to 3.6 V)

    • Low static power consumption; ICC = 0.9 μA (maximum)

    • Latch-up performance exceeds 100 mA per JESD 78 Class II

    • Overvoltage tolerant inputs to 3.6 V

    • Low noise overshoot and undershoot < 10 % of VCC

    • IOFF circuitry provides partial Power-down mode operation

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 3A exceeds 5000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    参数类型

    Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
    74AUP1G175GW-Q100Production0.8 - 3.6CMOS± 1.97.470ultra low-40~12526438.6153TSSOP6

    封装

    型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
    74AUP1G175GW-Q100
    TSSOP6
    (SOT363-2)     		SOT363-2SOT363-2_125ActiveaT74AUP1G175GW-Q100H
    ( 9353 005 11125 )

    环境信息

    型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
    74AUP1G175GW-Q10074AUP1G175GW-Q100H74AUP1G175GW-Q100Always Pb-free
    品质及可靠性免责声明

    文档 (7)

    文件名称标题类型日期
    74AUP1G175_Q100Low-power D-type flip-flop with reset; positive-edge triggerData sheet2023-08-03
    AN10161PicoGate Logic footprintsApplication note2002-10-29
    AN11052Pin FMEA for AUP familyApplication note2019-01-09
    aup1g175aup1g175 IBIS modelIBIS model2014-12-21
    Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Nexperia_document_leaflet_Logic_AUP_technology_portfolio_201904Leaflet2019-04-12
    Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
    SOT363-2plastic thin shrink small outline package; 6 leads; body width 1.25 mmPackage information2022-11-21

    支持

    如果您需要设计/技术支持，请告知我们并填写 应答表, 我们会尽快回复您。

    模型

    文件名称标题类型日期
    aup1g175aup1g175 IBIS modelIBIS model2014-12-21

    订购、定价与供货

    样品

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