The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OE _AB and OE _BA), and clock (CP_AB and CP_BA) inputs. For A-to-B data flow, the device operates in the transparent mode when LE_AB is HIGH. When LE_AB is LOW, the A data is latched if CP_AB is held at a HIGH or LOW logic level. If LE_AB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CP_AB. When OE _AB is LOW, the outputs are active. When OE _AB is HIGH, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CE _BA/CE _AB).

Data flow for B-to-A is similar to that of A-to-B but uses OE _BA,LE_BA and CP_BA.

To ensure the high-impedance state during power-down, OE _BA and OE _AB should be tied to V_CC through a pull-up resistor, the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

The 74ALVCH162601 is designed with 30 Ω series resistors in both HIGH or LOW output stage.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.