可订购部件
| 型号 | 可订购的器件编号 | 订购代码(12NC) | 封装 | 从经销商处购买 |
|---|---|---|---|---|
| 74HC73PW | 74HC73PW,118 | 935242070118 | SOT402-1 | 订单产品 |
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Click here for more information74HC73PW
Dual JK flip-flop with reset; negative-edge trigger
The 74HC73 is a dual negative edge triggered JK flip-flop with individual J, K, clock (nCP) and reset (nR) inputs and complementary nQ and nQ outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation. (nR) is asynchronous, when LOW it overrides the clock and data inputs, forcing the nQ output LOW and the nQ output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.
Features and benefits
CMOS low-power dissipation
- Wide supply voltage range from 2.0 to 6.0 V
- High noise immunity
- Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
- Complies with JEDEC standards
- JESD8C (2.7 V to 3.6 V)
- JESD7A (2.0 V to 6.0 V)
- ESD protection:
HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
Specified from -40 °C to +80 °C and from -40 °C to +125 °C
参数类型
| 型号 | Product status | VCC (V) | Logic switching levels | Output drive capability (mA) | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (°C) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HC73PW | Production | 2.0 - 6.0 | CMOS | ± 5.2 | 16 | 77 | low | -40~125 | 118 | 1.0 | 41.3 | TSSOP14 |
PCB Symbol, Footprint and 3D Model
| Model Name | 描述 |
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封装
| 型号 | 可订购的器件编号，（订购码(12NC)） | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
|---|---|---|---|---|---|---|---|
| 74HC73PW | 74HC73PW,118 (935242070118) |
Active | HC73 |
TSSOP14 (SOT402-1) |
SOT402-1 |
SSOP-TSSOP-VSO-WAVE
|
SOT402-1_118 |
文档 (11)
| 文件名称 | 标题 | 类型 | 日期 |
|---|---|---|---|
| 74HC73 | Dual JK flip-flop with reset; negative-edge trigger | Data sheet | 2024-03-26 |
| AN11044 | Pin FMEA 74HC/74HCT family | Application note | 2019-01-09 |
| SOT402-1 | 3D model for products with SOT402-1 package | Design support | 2023-02-02 |
| SOT402 | 3D model for products with SOT402 package | Design support | 2020-01-22 |
| Nexperia_package_poster | Nexperia package poster | Leaflet | 2020-05-15 |
| TSSOP14_SOT402-1_mk | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.1 mm body | Marcom graphics | 2017-01-28 |
| SOT402-1 | plastic, thin shrink small outline package; 14 leads; 0.65 mm pitch; 5 mm x 4.4 mm x 1.2 mm body | Package information | 2023-11-07 |
| SOT402-1_118 | TSSOP14; Reel pack for SMD, 13"; Q1/T1 product orientation | Packing information | 2020-04-21 |
| 74HC73PW_Nexperia_Product_Reliability | 74HC73PW Nexperia Product Reliability | Quality document | 2023-05-29 |
| HCT_USER_GUIDE | HC/T User Guide | User manual | 1997-10-31 |
| SSOP-TSSOP-VSO-WAVE | Footprint for wave soldering | Wave soldering | 2009-10-08 |
订购、定价与供货
| 型号 | Orderable part number | Ordering code (12NC) | 状态 | 包装 | Packing Quantity | 在线购买 |
|---|---|---|---|---|---|---|
| 74HC73PW | 74HC73PW,118 | 935242070118 | Active | SOT402-1_118 | 2,500 | 订单产品 |
样品
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How does it work?
The interactive datasheets are based on the Nexperia MOSFET precision electrothermal models. With our interactive datasheets you can simply specify your own conditions interactively. Start by changing the values of the conditions. You can do this by using the sliders in the condition fields. By dragging the sliders you will see how the MOSFET will perform at the new conditions set.
74HC73PW
Dual JK flip-flop with reset; negative-edge trigger
从安世半导体购买
| SKU | 库存* | MOQ | 单位价格 | 数量 |
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