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Click here for more information74AVC20T245DGG-Q100
20-bit dual supply translating transceiver with configurable voltage translation; 3-state
The 74AVC20T245-Q100 is a 20 bit, dual supply transceiver that enables bidirectional voltage level translation. The device can be used as two 10-bit transceivers or as a single 20-bit transceiver. It features four 10-bit input-output ports (1An, 1Bn, 2An, 2Bn) and two output enable inputs (nOE). It has two direction inputs (nDIR) and dual supplies (VCC(A) and VCC(B)). VCC(A) and VCC(B) can be independently supplied at any voltage between 0.8 V and 3.6 V. It makes the device suitable for bidirectional voltage level translation between any of the low voltage nodes: 0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V. The 1An and 2An ports, nOE and (nDIR) are referenced to VCC(A), the 1Bn and 2Bn ports are referenced to VCC(B). A HIGH on a 1DIR allows transmission from 1An to 1Bn and a LOW on 1DIR allows transmission from 1Bn to 1An. A HIGH on nOE causes the outputs to assume a HIGH impedance OFF-state.
The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, all output ports assume a high impedance OFF-state.
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.
Features and benefits
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Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Wide supply voltage range:
VCC(A): 0.8 V to 3.6 V
VCC(B): 0.8 V to 3.6 V
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Complies with JEDEC standards:
JESD8-12 (0.8 V to 1.3 V)
JESD8-11 (0.9 V to 1.65 V)
JESD8-7 (1.2 V to 1.95 V)
JESD8-5 (1.8 V to 2.7 V)
JESD8-B (2.7 V to 3.6 V)
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ESD protection:
MIL-STD-883, method 3015 Class 3B exceeds 8000 V
HBM JESD22-A114E Class 3B exceeds 8000 V
MM JESD22-A115-A exceeds 200 V (C = 200 PF, R = 0 Ω)
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Maximum data rates:
380 Mbit/s (≥ 1.8 V to 3.3 V translation)
260 Mbit/s (≥ 1.1 V to 3.3 V translation)
260 Mbit/s (≥ 1.1 V to 2.5 V translation)
210 Mbit/s (≥ 1.1 V to 1.8 V translation)
120 Mbit/s (≥ 1.1 V to 1.5 V translation)
100 Mbit/s (≥ 1.1 V to 1.2 V translation)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
IOFF circuitry provides partial Power-down mode operation
参数类型
型号 | Product status | Package name |
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74AVC20T245DGG-Q100 | End of life | TSSOP56 |
封装
下表中的所有产品型号均已停产 。
型号 | 可订购的器件编号,(订购码(12NC)) | 状态 | 标示 | 封装 | 外形图 | 回流焊/波峰焊 | 包装 |
---|---|---|---|---|---|---|---|
74AVC20T245DGG-Q100 | 74AVC20T245DGG-Q1J (935308525118) |
Obsolete | no package information |
Series
文档 (3)
文件名称 | 标题 | 类型 | 日期 |
---|---|---|---|
74AVC20T245_Q100 | 20-bit dual supply translating transceiver with configurable voltage translation; 3-state | Data sheet | 2019-01-15 |
AN90007 | Pin FMEA for AVC family | Application note | 2018-11-30 |
avc20t245 | 74AVC20T245 IBIS model | IBIS model | 2020-06-19 |
支持
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模型
文件名称 | 标题 | 类型 | 日期 |
---|---|---|---|
avc20t245 | 74AVC20T245 IBIS model | IBIS model | 2020-06-19 |
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