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74AVCH2T45-Q100

Dual-bit, dual-supply voltage level translator/transceiver; 3-state

The 74AVCH2T45-Q100 is a dual bit, dual supply transceiver that enables bidirectional level translation. It features two data input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins nA and DIR are referenced to VCC(A) and pins nB are referenced to VCC(B). A HIGH on DIR allows transmission from nA to nB and a LOW on DIR allows transmission from nB to nA.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are in the high-impedance OFF-state.

The 74AVCH2T45-Q100 has active bus hold circuitry which is provided to hold unused or floating data inputs at a valid logic level. This feature eliminates the need for external pull-up or pull-down resistors.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Wide supply voltage range: 0.8 V to 3.6 V for VCC(A) and VCC(B)

  • High noise immunity

  • Suspend mode

  • Bus hold on data inputs

  • Inputs accept voltages up to 3.6 V

  • Low noise overshoot and undershoot < 10 % of VCC

  • IOFF circuitry provides partial Power-down mode operation

  • Maximum data rates:

    • 500 Mbps (1.8 V to 3.3 V translation)

    • 320 Mbps (< 1.8 V to 3.3 V translation)

    • 320 Mbps (translate to 2.5 V or 1.8 V)

    • 280 Mbps (translate to 1.5 V)

    • 240 Mbps (translate to 1.2 V)

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/Jedec JS-001 Class 3B exceeds 8000 V

    • CDM: ANSI/ESDA/Jedec JS-002 Class C3 exceeds 1000 V

参数类型

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AVCH2T45DC-Q100Production0.8 - 3.60.8 - 3.6CMOS/LVTTL± 122.12very low-40~1252056.5115VSSOP8

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74AVCH2T45DC-Q100
VSSOP8
(SOT765-1) 		SOT765-1SOT765-1_125ActiveK4574AVCH2T45DC-Q100H
( 9356 914 45125 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74AVCH2T45DC-Q10074AVCH2T45DC-Q100H74AVCH2T45DC-Q100
品质及可靠性免责声明

文档 (2)

文件名称标题类型日期
74AVCH2T45_Q100Dual-bit, dual-supply voltage level translator/transceiver; 3-stateData sheet2022-12-07
SOT765-1plastic, very thin shrink small outline package; 8 leads; 0.5 mm pitch; 2 mm x 2.3 mm x 1 mm bodyPackage information2022-06-03

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