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74AVC4T774-Q100

4-bit dual supply translating transceiver; 3-state

The 74AVC4T774-Q100 is a 4-bit, dual supply transceiver that enables bidirectional level translation. It features eight 1-bit input-output ports (An and Bn), four direction control inputs (DIR1, DIR2, DIR3 and DIR4), an output enable input (OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any voltage between 0.8 V and 3.6 V making the device suitable for translating between any of the low voltage nodes (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V and 3.3 V). Pins An, OE and DIRn are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIRn allows transmission from An to Bn and a LOW on DIRn allows transmission from Bn to An. The output enable input (OE) can be used to disable the outputs so the buses are effectively isolated.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing any damaging backflow current through the device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both An and Bn are in the high-impedance OFF-state.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

特性

  • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

    • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

  • Wide supply voltage range:

    • VCC(A): 0.8 V to 3.6 V

    • VCC(B): 0.8 V to 3.6 V

  • Complies with JEDEC standards:

    • JESD8-12 (0.8 V to 1.3 V)

    • JESD8-11 (0.9 V to 1.65 V)

    • JESD8-7 (1.2 V to 1.95 V)

    • JESD8-5 (1.8 V to 2.7 V)

    • JESD8-B (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/Jedec JS-001 Class 3B exceeds 8000 V

    • CDM: ANSI/ESDA/Jedec JS-002 Class C3 exceeds 1500 V

  • Maximum data rates:

    • 380 Mbit/s (≥ 1.8 V to 3.3 V translation)

    • 200 Mbit/s (≥ 1.1 V to 3.3 V translation)

    • 200 Mbit/s (≥ 1.1 V to 2.5 V translation)

    • 200 Mbit/s (≥ 1.1 V to 1.8 V translation)

    • 150 Mbit/s (≥ 1.1 V to 1.5 V translation)

    • 100 Mbit/s (≥ 1.1 V to 1.2 V translation)

  • Suspend mode

  • Latch-up performance exceeds 100 mA per JESD 78 Class II

  • Inputs accept voltages up to 3.6 V

  • IOFF circuitry provides partial Power-down mode operation

参数类型

Type numberProduct statusVCC(A) (V)VCC(B) (V)Logic switching levelsOutput drive capability (mA)tpd (ns)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74AVC4T774BQ-Q100Production0.8 - 3.60.8 - 3.6CMOS/LVTTL± 122.14very low-40~1259213.061DHVQFN16
74AVC4T774GU-Q100Production0.8 - 3.60.8 - 3.6CMOS/LVTTL± 122.14very low-40~125994.187XQFN16

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74AVC4T774BQ-Q100
DHVQFN16
(SOT763-1) 		SOT763-1SOT763-1_115ActiveC4T77474AVC4T774BQ-Q100X
( 9356 913 31115 )
74AVC4T774GU-Q100
XQFN16
(SOT1161-1) 		SOT1161-1SOT1161-1_184ActiveStandard Marking74AVC4T774GU-Q100Z
( 9356 913 32184 )
SOT1161-1_115ActiveStandard Marking74AVC4T774GU-Q100X
( 9356 913 32115 )

环境信息

型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
74AVC4T774BQ-Q10074AVC4T774BQ-Q100X74AVC4T774BQ-Q100
74AVC4T774GU-Q10074AVC4T774GU-Q100Z74AVC4T774GU-Q100
74AVC4T774GU-Q10074AVC4T774GU-Q100X74AVC4T774GU-Q100
品质及可靠性免责声明

文档 (4)

文件名称标题类型日期
74AVC4T774_Q1004-bit dual supply translating transceiver; 3-stateData sheet2023-01-02
avc4t774AVC4T774 IBIS modelIBIS model2017-10-04
SOT763-1plastic, leadless dual in-line compatible thermal enhanced very thin quad flat package; 16 terminals; 0.5 mm pitch; 3.5 mm x 2.5 mm x 1 mm bodyPackage information2023-05-11
SOT1161-1plastic, leadless extermely thin quad flat package; 16 terminals; 0.4 mm pitch; 2.6 mm x 1.8 mm x 0.5 mm bodyPackage information2022-06-15

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模型

文件名称标题类型日期
avc4t774AVC4T774 IBIS modelIBIS model2017-10-04

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