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    74LVC1G10-Q100

    Single 3-input NAND gate

    The 74LVC1G10-Q100 provides a low-power, low-voltage single 3-input NAND gate.

    The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.

    Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall time.

    This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

    This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

    特性

    • Automotive product qualification in accordance with AEC-Q100 (Grade 1)

      • Specified from -40 °C to +85 °C and from -40 °C to +125 °C

    • Wide supply voltage range from 1.65 V to 5.5 V

    • High noise immunity

    • ±24 mA output drive (VCC = 3.0 V)

    • CMOS low power dissipation

    • Latch-up performance exceeds 250 mA

    • Direct interface with TTL levels

    • Inputs accept voltages up to 5 V

    • IOFF circuitry provides partial Power-down mode operation

    • Complies with JEDEC standard:

      • JESD8-7 (1.65 V to 1.95 V)

      • JESD8-5 (2.3 V to 2.7 V)

      • JESD8C (2.7 V to 3.6 V)

      • JESD36 (4.5 V to 5.5 V)

    • ESD protection:

      • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

      • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

    参数类型

    Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Nr of bitsPower dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
    74LVC1G10GW-Q100Production1.65 - 5.5CMOS/LVTTL± 322.61751low-40~12528456.2172TSSOP6

    封装

    型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
    74LVC1G10GW-Q100
    TSSOP6
    (SOT363-2)     		SOT363-2SOT363-2_125ActiveYM74LVC1G10GW-Q100H
    ( 9353 092 02125 )

    环境信息

    型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
    74LVC1G10GW-Q10074LVC1G10GW-Q100H74LVC1G10GW-Q100week 25, 2019
    品质及可靠性免责声明

    文档 (6)

    文件名称标题类型日期
    74LVC1G10_Q100Single 3-input NAND gateData sheet2023-08-14
    AN10161PicoGate Logic footprintsApplication note2002-10-29
    AN11009Pin FMEA for LVC familyApplication note2019-01-09
    lvc1g1074LVC1G10 IBIS modelIBIS model2014-10-20
    Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
    SOT363-2plastic thin shrink small outline package; 6 leads; body width 1.25 mmPackage information2022-11-21

    支持

    如果您需要设计/技术支持，请告知我们并填写 应答表, 我们会尽快回复您。

    模型

    文件名称标题类型日期
    lvc1g1074LVC1G10 IBIS modelIBIS model2014-10-20

    订购、定价与供货

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