NG体育娱乐，ng体育平台

×

74LVCH162374A

16-bit edge-triggered D-type flip-flop with 30 Ohm series termination resistors; 5 V input/output tolerant; 3-state

The 74LVCH162374A is a 16-bit edge triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus-oriented applications. The device consists of two sections of 8 edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided for each octal. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications. The flip-flops store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW to HIGH CP transition. When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused inputs.

To reduce line noise, 30 Ω series termination resistors are included in both high and low output stages.

特性

  • 5 V tolerant inputs/outputs for interfacing with 5 V logic

  • Wide supply voltage range from 1.2 V to 3.6 V

  • CMOS low power consumption

  • Multibyte flow-through standard pinout architecture

  • Multiple low inductance supply pins for minimum noise and ground bounce

  • Direct interface with TTL levels

  • All data inputs have bus hold

  • High-impedance outputs when VCC = 0 V

  • Complies with JEDEC standard:

    • JESD8-7A (1.65 V to 1.95 V)

    • JESD8-5A (2.3 V to 2.7 V)

    • JESD8-C/JESD36 (2.7 V to 3.6 V)

  • ESD protection:

    • HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

    • CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

  • Specified from -40 °C to +85 °C and -40 °C to +125 °C

参数类型

Type numberProduct statusVCC (V)Logic switching levelsOutput drive capability (mA)tpd (ns)fmax (MHz)Power dissipation considerationsTamb (°C)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package name
74LVCH162374ADGGProduction1.2 - 3.6CMOS/LVTTL± 243.8150low-40~125822.037TSSOP48

封装

型号封装尺寸版本回流焊/波峰焊包装状态标示可订购的器件编号，（订购码(12NC)）
74LVCH162374ADGG
TSSOP48
(SOT362-1) 		SOT362-1SSOP-TSSOP-VSO-WAVE
SOT362-1_118ActiveLVCH162374A74LVCH162374ADGG:1
( 9352 387 70118 )

停产信息

型号可订购的器件编号，（订购码(12NC)）最后一次购买日期最后一次交货日期替代产品状态备注
74LVCH162374ADGG935238770518
74LVCH162374ADGG935238770512
74LVCH162374ADGG9352387701122021-12-312022-06-3074LVCH162374ADGG

    环境信息

    型号可订购的器件编号化学成分RoHSRHF指示符无铅转换日期
    74LVCH162374ADGG74LVCH162374ADGG:174LVCH162374ADGGAlways Pb-free
    品质及可靠性免责声明

    文档 (7)

    文件名称标题类型日期
    74LVCH162374A16-bit edge-triggered D-type flip-flop with 30 Ohm series termination resistors; 5 V input/output tolerant; 3-stateData sheet2024-01-31
    AN263Power considerations when using CMOS and BiCMOS logic devicesApplication note2023-02-07
    AN11009Pin FMEA for LVC familyApplication note2019-01-09
    lvch162374alvch162374a IBIS modelIBIS model2013-04-07
    Nexperia_Selection_guide_2023Nexperia Selection Guide 2023Selection guide2023-05-10
    SSOP-TSSOP-VSO-WAVEFootprint for wave solderingWave soldering2009-10-08
    SOT362-1plastic thin shrink small outline package; 48 leads; body width 6.1 mmPackage information2024-01-05

    支持

    如果您需要设计/技术支持，请告知我们并填写 应答表, 我们会尽快回复您。

    模型

    文件名称标题类型日期
    lvch162374alvch162374a IBIS modelIBIS model2013-04-07

    订购、定价与供货

    样品

    安世半导体客户可通过我们的销售机构或直接通过在线样品商店订购样品： https://extranet.nexperia.com.

    样品订单通常需要2-4天寄送时间。

    如果您尚未取得安世半导体的直接采购帐号，我们的全球与区域经销网络可以协助您取得样品

    NG体育娱乐，ng体育平台